1. Field
The present disclosure relates to a regulator with enhanced slew rate.
The disclosure particularly, but not exclusively, relates to a regulator with another feedback network therein.
2. Description of the Related Art
A low-dropout (LDO) regulator is a DC linear voltage regulator which may be regulate an output voltage even when a supply voltage is very close to, the output voltage. Advantages of the LDO regulator over other DC to DC regulators include lower switching noise, smaller device size, and greater design simplicity.
FIG. 1 schematically shows a circuit diagram of a conventional LDO regulator 100. The LDO regulator 100 includes an operational amplifier 10, a PMOS transistor PM, a first resistor R1, and a second resistor R2. The operational amplifier 10 receives a reference voltage VCCI_REF at its inverting input node and a feedback voltage FEED at its non-inverting input node. The feedback voltage FEED is a voltage at a feedback node FEED between the first resistor R1 and the second resistor R2. The gate of the PMOS transistor PM is coupled with an output node of the operational amplifier 10. A source of the PMOS transistor PM is coupled to a power voltage PWR. A drain of the PMOS transistor PM is coupled with one node of the first resistor R1 at an output node VOUT. One node of the second resistor R2 is coupled with the other node of the first resistor R1 at the feedback node FEED and the other node of the second resistor R2 is coupled with a ground voltage VSSI.
The LDO regulator 100 employs a negative feedback network to stabilize an output voltage VOUT. The LDO regulator 100 operates as explained below.
The node of the output voltage VOUT is coupled to a load. When a high current is required from the load instantaneously the output voltage VOUT may be drop from its desired voltage slightly. The drop of the output voltage VOUT causes a drop of the feedback voltage FEED which is provided to the non-inverting input node of the operational amplifier 10. Then, the output voltage DVRP of the operational amplifier 10 starts to drop because the output voltage DVRP is a gain proportional to the difference of the feedback voltage FEED and the reference voltage VCCI_REF. The drop of the output voltage DVRP of the operational amplifier 10 controls the PMOS transistor PM so that the PMOS transistor PM may be flow, from its source to drain, enough current to recover the feedback voltage FEED to its desired voltage.
For a sudden voltage drop of the LOD regulator, its voltage needs to be recovered rapidly in a memory circuit, for example, because the memory of cutting edge technology operates in a quite high bandwidth. Late recovery of the regulator's output voltage may cause a critical malfunction in the memory device during different operations of a memory device (e.g., read, program, erase, data in, data out, and so forth).
To obtain fast recovery in the LDO regulator, it is required that the operational amplifier has a high slew rate and a high bandwidth. However, the high slew rate and bandwidth will increase current consumption. Moreover, there is a trade-off between gain and bandwidth, thus increasing bandwidth of the operational amplifier may reduce the gain of it. High gain of the operational amplifier 10 is necessary to sense a small amount of voltage, drop.
It is needed to devise an improved LDO regulator capable of operating with high slew rate without much current consumption increase.